Different types of memory are used in electronic apparatus for various purposes. Read-only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device includes an array of addressable memory cells arranged in columns and rows. A typical SRAM cell includes two access transistors and a flip-flop formed with two cross-coupled inverters. Each inverter has a pull-down (driver) and a pull-up (load) transistor. The gates of the access transistors in each row are connected to a word line and the sources of each of the access transistors in each column are connected to either one of a pair of complementary bit lines, BL or BL_. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the SRAM cells.
Generally, an SRAM block is configured to store multiple words on each row, with each word comprising multiple bits, such that the multiple bits of a single word are read or written in a single cycle. In either a read or a write cycle, one word line is turned on, as selected by the row address. All bits in the selected row are then accessed to the associated bit line pairs.
Generally, to read data from an SRAM cell, a word line driver activates a word line according to an address decoded by a row decoder and received via a control signal path that typically includes an address bus connected to the SRAM device. The access transistors of all the cells in the addressed row turn on and connect the outputs of the flip-flop to the bit line pair. Generally, the bit lines are precharged high and one or the other of each bit line pair is pulled low by the accessed cell, creating a differential voltage on each bit line pair. The cell is designed so that with the bit lines precharged high, the accessed cells are not upset by the charge on the bit lines. With n-channel access transistors in the cell, the bit lines are precharged high to within about the threshold voltage of the access transistor relative to the selected on word line voltage to be robust against cell upset. Also, with higher bit line precharge voltage, the current through the cell access transistor is greater and the differential voltage on the bit line pair is established more quickly. The differential voltages from bit line pairs selected by the word of column address are connected to sense amplifiers. The sense amplifier produces a logical 0 or 1 from the potential difference on the bit line pair, which is, in turn, provided to external circuitry of the associated electronic apparatus, perhaps through a buffer.
In a write cycle, the bit lines are precharged high, one word line is turned on, and one or the other of bit line pairs selected by the word or column address is pulled low by the write drivers to force the state of the selected cells. With the bit line pairs precharged high, the cells in the accessed row that are not written into are not upset, just as in the read cycle.
As mentioned above, to retain the data written to the SRAM array, each SRAM cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, SRAM devices are often capable of operating in multiple modes, each mode representing a tradeoff in terms of speed and power consumption. One such mode is the active mode. In the active mode, the SRAM array and surrounding read and write circuitry are provided full power. The array and circuitry are therefore ready for operation at all times, and read and write speed is the fastest. Another mode is the inactive, or sleep, mode. In the inactive mode, the SRAM array is provided power so as not to lose data, but all of the surrounding read and write circuitry are turned off. The surrounding read and write circuitry must be turned back on before reading or writing can occur, and so a latency occurs in initiating a read or write access.
Another mode of operation represents a middle ground between active mode and inactive mode. Retain Till Accessed (RTA) mode calls for the read and write circuitry to remain powered. The SRAM array itself is powered at a reduced voltage sufficient to retain the stored data, but insufficient to allow reliable read or write access. When a read and write access is to be done, only the cells needed for the access are activated; the remaining cells are retained at lower voltage.
Though the RTA mode represents a decrease in latency over the inactive mode, keeping the peripheral circuitry powered reduces the power savings relative to the inactive mode. In particular, keeping the bit lines precharged adds to the power. In the inactive mode, bit lines are typically left to float for lowest power. Left to their own, the bit lines float down to near Vss, which is effectively ground for the SRAM device. To be reactivated, they need to be precharged to Vdd, which is the operating voltage of the SRAM device. Since the bit lines generally have relatively large capacitance, recharging the bit lines from near Vss to Vdd would add undesirable latency and dynamic power to RTA mode operation.
Accordingly, what is needed in the art is a way to control the voltage of the bit lines in an RTA mode such that power is reduced without an unacceptable increase in latency or dynamic power.